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1 of 22 proprietary & confidential gs3490 final data sheet rev. 1 gendoc-058568 april 2014 gennum products gs3490 configurable adaptive cable equalizer/cable driver www.semtech.com key features ? connection to a single bnc connector as an adaptive cable equalizer or cable driver ? performance and cable reach optimized for smpte st 424, smpte st 29 2, and smpte st 259 data rates ? multi-rate operation from 125mb/s to 2.97gb/s in equalizer mode and 270mb/s to 2.97gb/s in cable driver mode ? supports dvb-asi at 270mb/s ? integrated 100 , differential digital data input/output termination ? low power operation from a single 3.3v supply: ? 206mw typical power consumption in eq mode ? 190mw typical power consumption in cd mode ? temperature range: -40c to +85c ? 32-pin 5mm x 5mm qfn package cable equalizer features ? integrated cable equalizer: ? 140m - 3g ? 260m - hd ? 500m - sd ? carrier detect with adju stable squelch threshold ? optional automatic power-down on loss of input signal cable driver features ? selectable output slew rate cable driver for compliance with smpte st 424, smpte st 292, and smpte st 259 standards applications ? smpte st 424, smpte st 292 and smpte st 259 interfaces requiring switching between cable equalizing or cable driving functionality description the gs3490 features integrated adaptive cable equalizer and cable driver functionality. the gs3490 can be field-configured as a smpte compliant cable equalizer or a smpte compliant cable driver. the gs3490 is optimized for ap plications with limited i/o space. with its configur able eq and cable driver functionality, the gs3490 can be utilized as a single-device solution in applications where the interface connector can be configured as either an input or output. the gs3490's cable equalizer is optimized for operation at 2.97gb/s, 1.485gb/s and 270mb/s while providing typical cable reach of 140m at 2.97gb/s, 260m at 1.485gb/s and 500m at 270mb/s. in cable driver mode, the dual sl ew rate capability provides compatibility to smpte st 424, smpte st 292 and smpte st 259 interfaces. gs3490 block diagram cd eq eq_op_ctrl eq_bypass sdi/sdo eq_disable cd_sd_en rset cd_enable cd ddo ddi ddi ddo eq_sq_adj eq_gain_sel
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 2 of 22 proprietary & confidential www.semtech.com revision history contents 1. pin out..................................................................................................................... ............................................3 1.1 pin assignment ............................................................................................................ .......................3 1.2 pin descriptions .......................................................................................................... ........................3 2. electrical characteristics.................................................................................................. ..............................6 2.1 absolute maximum ratings .................................................................................................. .........6 2.2 dc electrical characteristics ............................................................................................. ..............6 2.3 ac electrical characteristics ............................................................................................. ...............8 3. input/output circuits....................................................................................................... ........................... 10 4. detailed description........................................................................................................ ............................ 13 4.1 equalizer mode ............................................................................................................ ..................... 13 4.1.1 equalizer mode enable.................................................................................................... .. 13 4.1.2 serial digital inputs (sdi/sdi ).......................................................................................... 13 4.1.3 automatic (adaptive) cable equalization .................................................................. 13 4.1.4 carrier detect (cd ) .............................................................................................................. 14 4.1.5 squelch adjust (eq_sq_adj) ......................................................................................... 14 4.1.6 differential digital data outputs (ddo/ddo ).......................................................... 14 4.1.7 adjustable output swing, de-emphasis and mute (eq_op_ctl)..................... 15 4.2 cable driver mode ......................................................................................................... ................. 16 4.2.1 cable driver mode enable................................................................................................ 1 6 4.2.2 differential digita l data inputs (ddi/ddi ) .................................................................. 16 4.2.3 serial data outputs (sdo/sdo ) ..................................................................................... 16 4.2.4 slew rate selection (cd_sd_en)................................................................................... 17 4.2.5 output amplitude (r set )................................................................................................... 17 5. application information..................................................................................................... ........................ 18 5.1 typical application circuit ............................................................................................... ............ 18 5.2 pcb layout ................................................................................................................ ......................... 18 6. package & ordering information .............................................................................................. .............. 19 6.1 package dimensions ........................................................................................................ .............. 19 6.2 packaging data ............................................................................................................ .................... 20 6.3 recommended pcb footprint ................................................................................................. ... 20 6.4 marking diagram ........................................................................................................... .................. 21 6.5 solder reflow profiles .................................................................................................... ................ 21 6.6 ordering information ...................................................................................................... ............... 21 version eco pcn date changes and/or modifications 1 019093 april 2014 converted to final data sheet. updated common mode voltage specifications. 0 015642 september 2013 updated to preliminary data sheet. default state of cd_enable corrected. b 011682 march 2013 updates throughout the document. a 158716 october 2012 new document.
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 3 of 22 proprietary & confidential www.semtech.com 1. pin out 1.1 pin assignment figure 1-1: pin out 1.2 pin descriptions 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 17 gs3490 32-pin qfn (top view) ground pad (bottom of package) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vee sdo vee vee sdi eq_gain_sel agc vee nc eq_bypass eq_sq_adj eq_op_ctl cd_sd_en vee ddo vee vee ddi vcc vcc vcc cd_enable eq_disable rset vcc vee cd ddo sdo ddi sdi agc table 1-1: gs3490 pin descriptions pin number name type description 1, 4, 5, 11, 20, 21, 24, 25 vee power most negative power supply connection. connect to gnd. 2, 3 sdo /sdo output serial data output. 6, 7 sdi/sdi input serial data input.
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 4 of 22 proprietary & confidential www.semtech.com 8 eq_gain_sel input input sensitivity control. please refer to the input logic parameter in table 2-2: dc electrical characteristics for logic level threshold and compatibility. this pin is a 3.3v input. when high, the device compensates for an additional 6db of loss across the entire operating band. this pin has an internal 100k pull-down resistor. 9, 10 agc/agc external agc capacitor connection. 12 nc no connect. not bonded internally. 13 eq_bypass input equalizer bypass control. please refer to the input logic parameter in table 2-2 for logic level threshold and compatibility. for details on operation, refer to section 4.1.3 . this pin has an internal 100k pull-down resistor. 14 eq_sq_adj input squelch threshold adjust. for details on operation, refer to section 4.1.5 . this pin has an internal 82.4k pull-down resistor. 15 eq_op_ctl input controls the output swing, de-emphasis and mute features of the ddo/ddo outputs. for details on operation, refer to section 4.1.7 . this pin has an internal 1m pull-down resistor. 16 cd_sd_en input cable driver slew rate control. for details on operation, refer to section 4.2.4 . when left unconnected, the default state of this pin is logic high 17, 26, 31, 32 vcc power most positive power supply connection. connect to 3.3v dc. 18, 19 ddi/ddi input differential digital data input to cable driver core. 22, 23 ddo /ddo output differential digital data output from cable equalizer core. 27 rset external cable driver output amplitude control resistor connection. 28 eq_disable input equalizer mode disable control. please refer to the input logic parameter in table 2-2 for logic level threshold and compatibility. for details on operation, refer to section 4.1.1 . this pin has an internal 100k pull-down resistor. table 1-1: gs3490 pin descriptions (continued) pin number name type description
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 5 of 22 proprietary & confidential www.semtech.com 29 cd_enable input cable driver mode enable control. please refer to the input logic parameter in table 2-2 for logic level threshold and compatibility. for details on operation, refer to section 4.2.1 . when left unconnected, the default state of this pin is logic low. 30 cd output equalizer carrier detect status output. please refer to the output logic parameter in table 2-2 for logic level threshold and compatibility. for details on operation, refer to section 4.1.4 . center pad power internally bonded to vee. for more details, refer to section 6.3 . table 1-1: gs3490 pin descriptions (continued) pin number name type description
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 6 of 22 proprietary & confidential www.semtech.com 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value supply voltage -0.5v to 3.6v dc input esd voltage (hbm) 3kv storage temperature range -50c to 125c input voltage range (any input) -0.3 to (v cc + 0.3)v dc operating temperature range -40c to +85c solder reflow temperature 260c note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation outside of th e ranges shown in the ac/dc electrical characteristics tables is not guaranteed. table 2-2: dc electrical characteristics v cc = +3.3v 5%, t a = -20 c to +85 c (unless otherwise shown), fun c tional temperature ran g e: -40 c to +85 c parameter symbol conditions min typ max units notes supply voltage v cc C 3.135 3.3 3.465 v C power consumption p d equalizer mode ddo output swing = 425mv ppd C 206 248 mw 4 equalizer mode ddo output swing = 850mv ppd C 244 289 mw 4 cable driver mode C 190 235 mw 1 power-down mode eq_disable = 1, cd_enable = 0 C3956mwC supply current i s equalizer mode ddo output swing = 425mv ppd C6577ma 3 equalizer mode ddo output swing = 850mv ppd C7487ma 3 cable driver mode C 58 68 ma 1 power-down mode eq_disable = 1, cd_enable = 0 C1217maC
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 7 of 22 proprietary & confidential www.semtech.com cd output voltage v cd (oh) carrier not present 2.0 C C v C v cd (ol) carrier present C C 0.4 v C input voltage - digital pins v eq_bypass, v eq_disable, v eq_gain_sel, v cd_sd_en, v cd_enable minimum to assert and maximum to de-assert 1.7 C 0.4 v C sdi/sdi common mode voltage v cmin common mode 1.62 1.71 1.80 v C ddo/ddo common mode voltage v cmddo common mode see section 4.1.6 vC ddi/ddi common mode voltage v cmddi common mode ac-coupled 1.4 + v ddi / 4 C v cc C v ddi / 4 vC sdo/sdo common mode voltage v cmout common mode ac-coupled C v term - v sdo Cv 2 notes: 1. power consumed by gs3490 only. termination resistors draw extra current. 2. refer to 4.2.3 serial data outputs (sdo/sdo) . 3. de-emphasis off. with de-emphasis en abled, add 3ma at typical conditions. 4. de-emphasis off. with de-emphasis enabled, add 10mw at typical conditions. table 2-2: dc electrical characteristics (continued) v cc = +3.3v 5%, t a = -20 c to +85 c (unless otherwise shown), fun c tional temperature ran g e: -40 c to +85 c parameter symbol conditions min typ max units notes
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 8 of 22 proprietary & confidential www.semtech.com 2.3 ac electrical characteristics table 2-3: ac electrical char acteristics - equalizer mode v cc = +3.3v 5%, t a = -20 c to +85 c (unless otherwise shown), fun c tional temperature ran g e: -40 c to +85 c parameter symbol conditions min typ max units notes serial data rate dr sdi C 125 C 2970 mb/s 1 sdi/sdi input voltage swing v sdi 270mb/s and 1.485gb/s 720 800 950 mv ppd 2 2.97gb/s 720 800 880 mv ppd 2 ddo/ddo output voltage swing v ddo 100 load, eq_op_ctl set for high swing 700 850 1000 mv ppd C 100 load, eq_op_ctl set for low swing 350 425 500 mv ppd C ddo/ddo output jitter C 2.97gb/s belden 1694a: 0-140m C 0.2 0.45 ui 3 , 4 1.485gb/s belden 1694a: 0-200m C C 0.2 ui 3 , 4 1.485gb/s belden 1694a: 200-260m C 0.3 0.4 ui 3 , 4 270mb/s belden 1694a: 0-300m C 0.1 0.2 ui 3 , 4 270mb/s belden 1694a: 300-500m C 0.2 0.3 ui 3 , 4 ddo/ddo rise/fall time t r , t f 1.485gb/s and 2.97gb/s, 20% - 80% C 75 C ps C 270mb/s, 20% - 80% C 150 C ps C mismatch in rise/fall time t r , t f CCC30psC duty cycle distortion C sd/hd/3g C C 30 ps C overshoot C C C C 10 % C input return loss C 5mhz - 1.485ghz 15 C C db 5 1.485ghz - 2.97ghz 10 C C db 5 sdi/sdi input resistance C single-ended C 1.9 C k C sdi/sdi input capacitance Csingle-ended C 1.3 C pf C ddo/ddo output resistance Csingle-ended C 50 C w C equalizer mode enable delay CC C 1 C s C notes: 1. device performance is optimized for standard data rates (sd = 270mb/s, hd = 1.485gb/s, 3g = 2.970gb/s). 2. 0m cable length. 3. all parts are production tested. in order to guarantee jitter over the full range of specification (v cc = 3.3v 5%, t a = -40c to +85c, and 720-880mv launch swing from a smpte compliant cable driv er) the recommended applications circuit must be used. 4. based on validation data using the recommended circuit, at v cc = 3.3v, t a = 25c and 800mv launch swing from a smpte compliant cable driver. 5. irl depends on board design. the gs3490 achieves this specification on semtechs evaluation boards.
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 9 of 22 proprietary & confidential www.semtech.com table 2-4: ac electrical charac teristics - cable driver mode v cc = +3.3v 5%, t a = -20 c to +85 c (unless otherwise shown), fun c tional temperature ran g e: -40 c to +85 c parameter symbol conditions min typ max units notes serial data rate dr ddi C 270 C 2970 mb/s C additive jitter C 2.97gb/s C 15 25 ps pp C 1.485gb/s C 15 25 ps pp C 270mb/s C 55 85 ps pp C sdo rise/fall time t r , t f cd_sd_en = 0, 20% - 80% C C 135 ps C t r , t f cd_sd_en = 1, 20% - 80% 400 C 950 ps C mismatch in rise/fall time t r , t f cd_sd_en = 0 only C C 35 ps C duty cycle distortion C cd_sd_en = 0, 2.97gb/s C C 14 ps 1 , 2 cd_sd_en= 0, 1.485gb/s C C 20 ps 1 , 2 cd_sd_en = 1 C C 50 ps 1 , 2 overshoot C cd_sd_en = 0 C C 10 % 1 output return loss orl 5mhz - 1.485ghz 15 C C db 3 1.485ghz - 2.97ghz 10 C C db 3 sdo output voltage swing v sdo r set = 750 750 800 880 mv pp 1 ddi/ddi input voltage swing v ddi guaranteed functional 100 C 250 mv ppd C guaranteed to meet all published specifications 250 C 2200 mv ppd C cable driver mode enable delay CC C 0.25 C s C notes: 1. single-ended into 75 external load. 2. calculated as the actual positive bit-width compared to the expected positive bit-width using a 1010 pattern. 3. orl depends on board design. the gs3490 achieves this specification on semtech's evaluation boards.
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 10 of 22 proprietary & confidential www.semtech.com 3. input/output circuits figure 3-1: equalizer serial digital input circuit figure 3-2: eq_sq_adj circuit figure 3-3: equalizer differential digital data output circuit 2.625k rc sdi sdi rc 2k 2k 2k vcc 82.4k + - eq_sq_adj 50 50 ddo ddo vcc vcc vcc
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 11 of 22 proprietary & confidential www.semtech.com figure 3-4: eq_disable, eq_bypass, eq_gain_sel circuits figure 3-5: cd circuit eq_disable, eq_bypass, eq_gain_sel 100k vcc cd internal 2.5v figure 3-6: eq_op_ctl circuit figure 3-7: cable driver diffe rential digital data input circuit vcc internal reference internal reference eq_op_ctl internal circuitry 1m vcc vcc ddi ddi 50 50 5k 10k eq rc* vcc 700pf *rc network for trace equalization
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 12 of 22 proprietary & confidential www.semtech.com figure 3-8: cable driver se rial digital output circuit figure 3-9: cd_sd_en circuit figure 3-10: cd_enable circuit vcc i ref sdo sdo vcc in vref pull-up 80a typical (50-150a) in vref pull-down 80a typical (50-150a)
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 13 of 22 proprietary & confidential www.semtech.com 4. detailed description the gs3490 is a half-duplex, bi-directional de vice that integrates the functions of both a cable equalizer and a cable driver in one package, allowing for a single application circuit to perform both functions through a single bnc connector. the gs3490 pin out enables switching from one mode to another using a si ngle logic control signal. 4.1 equalizer mode 4.1.1 equalizer mode enable to enable equalizer mode, both the eq_disable and cd_enable pins must be set to logic low. these two pins may be tied toge ther and controlled from a single logic signal. 4.1.2 serial digital inputs (sdi/ sdi ) please refer to section 5.1 for the correct way to implement the bi-directional serial input/output. other application circuits are not supported. 4.1.3 automatic (adaptive) cable equalization the gs3490 automatically adjust s its gain to equalize and re store signals received over different lengths of coaxial cable having loss characteristics similar to belden 8281 or 1694a. the device is designed to automatically equalize smpte sdi signal rates from 125mb/s up to 2.97gb/s and dvb-asi signals at 270mb/s. the equalized signal is dc-restored, effe ctively restoring the logic threshold of the equalized signal to its correct level in dependent of shifts due to ac-coupling. adaptive cable equalization and dc restoration can be disabled by pulling the eq_bypass pin high. table 4-1: gs3490 operating modes eq_disable cd_enable description 00equalizer mode 0 1 debug mode* 1 0 power-down mode 1 1 cable driver mode *note: data represented at the cable drivers digital data input is passed through the device, looped back through the equalizer and appears on the equalizers digital data output. the data is looped through the device, provided the sdi/o bnc is terminated with a 75 load that is not driving a signal.
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 14 of 22 proprietary & confidential www.semtech.com 4.1.4 carrier detect ( cd ) the carrier detect output pin (cd ) indicates the presence of a signal at the input of the gs3490. when cd is low, the device has detect ed an input on its sdi/sdi pins. when cd is high, the device has not detected an input signal. when eq_disable is high, the cd output will still function to facilitate the detection of a serial input data signal. as a result, when in equalizer mode, auto power-down can be implemented by directly tying cd to eq_disable. when connected, the gs3490 will automatically go into lower power mode when there is a loss of serial digital input signal. note 1: cd will only operate correctly for data rates greater than 19mb/s. note 2: if eq_sq_adj is being used to limit the maximum gain of the device, and the maximum cable length is exceeded when eq_bypass pin is set low, the cd pin will be set high even if a carrier is present. note 3: if the cd pin is connected to the eq_disable pin, eq_sq_adj must be either left open, or connected to ground. 4.1.5 squelch adjust (eq_sq_adj) the gs3490 features a squelch adjust (eq_sq_adj) threshold. this feature can be useful in applications where there are multiple input channels using the gs3490, since the maximum gain can be limited to avoid crosstalk. the eq_sq_adj pin acts to change the threshold of the carrier detect (cd ) pin, through voltage level variances. when the input signal drops belo w a certain threshold, the cd pin will be driven high, indicating that there is not a valid input signal. in applications where squelch adjust is not required, the eq_sq_adj pin can be left unconnected. this feature has been designed for use in applications, where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. the use of a carrier detect function with a fixe d internal reference does not solve this problem, since the signal-to-noise ratio on th e circuit board could be significantly less than the default signal detection level set by the on-chip reference. note: when using eq_sq_adj to limit the maximum gain of the gs3490, auto power-down is not supported and so cd should not be connected to eq_disable. 4.1.6 differential digital data outputs (ddo/ ddo ) the digital data output signals have a nomi nal output voltage swing of either 850mv ppd or 425mv ppd , as set by the eq_op_ctl pin. when eq_disable is high, the differential digital outputs are high impedance and will be pulled high by the on-chip termination. table 4-2 shows the typical output common mode voltage levels (v cmddo ) related to the two output swing option s and the type of output transmission termination as shown in figure 4-1 and figure 4-2 .
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 15 of 22 proprietary & confidential www.semtech.com 4.1.7 adjustable output swing, de-emphasis and mute (eq_op_ctl) the eq_op_ctl input pin determines the ou tput swing and de-emphasis settings for ddo/ddo . the eq_op_ctl pin is an analog input allowi ng different combinations of output swing, de-emphasis and mute. the possible values are listed in table 4-3 below: table 4-2: typical common mode output voltage levels (v cmddo ) - vcc = 3.3v output voltage swing ( v ddo ) termination type 1 (see figure 4-1 ) termination type 2 (see figure 4-2 ) 425mv ppd 3.09v 3.19v 850mv ppd 2.88v 3.09v figure 4-1: 100 parallel output termination figure 4-2: 50 termination to vcc 100 50 50 50 50 ddo vcc 5 0 5 0 dd o v cc gs3490 ddo 50 50 ddo vcc 50 50 gs3490 vcc vcc 50 50 ddo 5 0 5 0 dd o v cc gs3 4 90 dd o table 4-3: eq_op_ctl functions and levels level swing (mv ppd ) de-emphasis mute voltage (v) 0 850 off n 0.000 - 0.083 1 850 2db n 0.234 - 0.394 2 850 4db n 0.545 - 0.704 3 850 6db n 0.856 - 1.015 4 425 off n 1.166 - 1.333 5 425 2db n 1.484 - 1.644 6 425 4db n 1.795 - 1.954 7 425 6db n 2.106 - 2.265 8 425 n/a y 2.416 - 2.500
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 16 of 22 proprietary & confidential www.semtech.com when muted, the output swing is set to 425mv ppd and the ddo/ddo outputs are latched. automatic muting of the output ca n be enabled by connecting the cd pin to the eq_op_ctl pin. if the connection is made directly, as shown in figure 4-3 , the output would be in its default mode (850mv ppd swing with no de-emphasis) wh en there is a signal present. figure 4-3: direct loopback 4.2 cable driver mode 4.2.1 cable driver mode enable to enable cable driver mode, eq_disable and cd_enable must be set to logic high. these two pins may be tied together and controlled from a single logic signal. 4.2.2 differential digital data inputs (ddi/ ddi ) the gs3490 features a differential input buffer (ddi/ddi ) with on-chip 100 differential termination. the differential data input signal is connected to the ddi and ddi input pins of the device. the serial data input buffer is capable of operation with any binary coded signal that meets the input signal level requirements, in the range of 270mb/s to 2.97gb/s in cable driver mode. the input circuit is self-biasing to allow for simple ac or dc-coupling of input signals to the device. 4.2.3 serial data outputs (sdo/ sdo ) the gs3490 features a current-mode differential output driver capable of achieving output swings up to 1040mv pp using a 3.3v termination supply (v term ). the output signal amplitude or sw ing is set using an external r set resistor. for the most commonly used output swing conf igurations, please refer to section 4.2.5 . the sdo/sdo pins of the device provide the serial data outputs. please refer to section 5.1 for the correct way to implement the bi-directional serial input/output. other application circuits are not supported. eq_op_ctl cd
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 17 of 22 proprietary & confidential www.semtech.com 4.2.4 slew rate selection (cd_sd_en) the gs3490 supports two output slew rates on sdo/sdo . control of the slew rate is determined by the setting of the cd_sd_en input pin. 4.2.5 output amplitude (r set ) the output amplitude of the gs3490 can be adjusted by changing the value of the r set resistor as shown in table 4-5 . for an 800mv pp output with a nominal 7% tolerance, a value of 750 is required. a 1% smt re sistor should be used. the r set resistor is part of an internal dc fe edback loop in the gs3490. the resistor should be placed as close as possible to the rset pin, and connected directly to the vcc plane with more than one via to minimi ze inductance (traces/wires may cause instability). note: care should be taken when considering layout of the r set resistor. please refer to section 5.2 for more details. note 1: actual swing values may vary based on layout. note 2: r set is the resistor connected fr om pin 27 to vcc (refer to figure 5-1 ). note 3: r term is the sdo/sdo pull up resistor. table 4-4: slew rate selection cd_sd_en rise/fall time 0 smpte st 424 & smpte st 292 compliant 1 smpte st 259 compliant floating smpte st 259 compliant table 4-5: typical r set values output swing (mv pp ) r set ( ) r term ( ) v term (v) 1040 576 75 3.3 800 750 75 3.3 500 1210 75 3.3
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 18 of 22 proprietary & confidential www.semtech.com 5. application information 5.1 typical application circuit figure 5-1: gs3490 typical application circuit 5.2 pcb layout special attention must be pa id to component layout when designing serial digital interfaces for hdtv. a fr-4 dielectric ca n be used, however, controlled impedance transmission lines are required for pcb traces longer than approximately 1cm. note the following pcb artwork features used to optimize performance: ? pcb trace width for 3gb/s rate signals is closely matched to smt component width to minimize reflections due to change in trace impedance. ? high-speed traces are curved to minimize impedance changes. cutouts in the inner layers should be used under the gs3490 input and output components to minimize parasitic capacitance. for more detail on this and other layout recommendations, please refer to a guide for designing with semtech's 3g-sdi equalizers (doc id: gendoc-055280). sdi/o 750 470nf 137 4.7f 1f 10nf 7.5nh 1f 75 vcc vcc 100 75 vcc 75 u2 5 4 25 24 21 20 11 1 32 31 26 tab 3 2 6 7 27 12 30 10 9 8.2nh 4.7f 17 gs3490 tab vcc vcc vcc vee vee vee vee vee vee vee vee cd 29 cd_enable 28 eq_disable rset ddo ddo ddi ddi 16 cd_sd_en 15 eq_op_ctl 14 eq_sq_adj 13 eq_bypass nc agc- agc+ sdi sdi sdo sdo vcc 10nf 10nf 10nf 10nf 75 note: ac-coupling capacitors may be required on ddi/ddi and ddo/ddo when interfacing to devices with incompatible common mode voltages. 18 19 23 22 8.2nh 8 eq_gain_sel
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 19 of 22 proprietary & confidential www.semtech.com 6. package & ordering information 6.1 package dimensions figure 6-1: packaging dimensions pin 1 area 5.00 a b 5.00 0.400.05 3.500.10 0.30x45 detail a 0.250.05 r0.50 ref (3x) 0.50 datum b 3.500.10 datum a or b terminal tip 0.50 0.50/2 detail a 0.900.10 0.02 + 0.03 0.08 0.10 c c c 2x 2x 32x 0.10 0.05 ca b c datum a 0.20 ref 0.15 c c 0.15 32x seating plane - 0.02 note: all dimensions in mm, angles in degrees dimensioning and tolerancing conform to asme y14.5 1994
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 20 of 22 proprietary & confidential www.semtech.com 6.2 packaging data 6.3 recommended pcb footprint figure 6-2: recommended pcb footprint parameter value package type 32-pin qfn / 5mm x 5mm / 0.5mm pad pitch moisture sensitivity level 3 junction to case thermal resistance, j-c 17.8c/w junction to air thermal resistance, j-a (at zero airflow) 26.4c/w psi ( ) =junction-to-top (of package) characterization parameter 0.4c/w pb-free and rohs compliant yes 0.6 0.3 0.50 4.20 3.30 0.40 x 45 notes: 1. all dimensions in mm. 2. drawing not to scale. 3. 16 thermal vias, evenly spaced on centre paddle connected to ground plane. pin #1
gs3490 final data sheet rev. 1 gendoc-058568 april 2014 21 of 22 proprietary & confidential www.semtech.com 6.4 marking diagram figure 6-3: marking diagram 6.5 solder reflow profiles figure 6-4: maximum pb-free solder reflow profile 6.6 ordering information gs3490 xxxxe3 yyww pin 1 id xxxx - last 4 d i g its (ex c lu d in g d e c imal) of s ap bat c h assem b ly (fin) as liste d on pa c kin g s lip. e3 - p b -free & g reen in d i c ator yyww - date c o d e 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max part part number package temperature range gs3490 GS3490-INE3 32-pin qfn -40c to 85c
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